Register locations for LM104 board and how it is used in code.
Following code is from MIP_TYPS.H lines 44-64

// Hardware Interface I/O Ports:
// The registers io_port_num and io_port_num provide direct
// access to the MIP's parallel port and will pulse the MIP's CS
// input when read/written.
// The four bits of status appear in io_port_num+1.
// and io_port_num+1 will either reset the MIP or clear the status
// flags (RESET, DMA_END, and UL_INT).
// On the LM-104, DMA is not supported so the DMA_END bit is ignored

//#define RISR_DMA_END		0x02    

#define RISR_RESET		0x01
#define RISR_HS			0x02
#define RISR_UL_INT		0x04	

#define WCNTL_RESET		0x01	// For h.w. reset of the MIP
#define WCNTL_CLR_FLGS		0x06	// For clearing status flags
#define WCNTL_CLR_ALL		0x07	// For clearing status and 
					// resetting MIP


In plain english this means:
D0
 read=RST_L, reset latch is set (board has been reset)
 write=reset, causes a reset (neuron reset pin pulled low)
D1
 read=HS
 write=RST_L, clear reset latch
D2
 read=IRQ_L interupt latch is set
 write=IRQ_L clear interupt latch

The word "latch" can be replaced with the word "flag" for software people.
All actions or status is active high.

